Dac discrete R2R soekris@diyaudio

DAC R2R (résistances discrètes) à un tarif ultra-concurrentiel (les DACs en composants discrets avec une résolution >= 24bits premier-prix sont vendus à plusieurs milliers d'euros !).

En résumé :


Dimensions : 81 x 147 mm


2 x 7-15V DC or AC. Designed for single 2 x 7-8V 5W toroid transformer.


i2s + SPDIF ; possibilité de mettre une interface i2s/USB



En pas résumé :

Entrée sortie

Entrées: 1 entrée I2S galvaniquement isolé 3 entrée S/Pdif balanced: jusqu'à 3 entrée Coaxial/Optique/AES EBU

- JTAG - pour mise à jour du firmware

Sorties Balanced


Le FPGA est le maitre des clés: il est reponsable de la transformation du signal SPDIF en i2s - de l'oversampling et du reclocking en FIFO.

L'oversampling monte à 3 mega samples par seconde sur le prototype, le concepteur pense que 6Msps est possible avec une fréquence d'horloge de 100mhz, mais qu'il ne le fera probabelment pas. on pourra customiser ou désactiver l'oversampling et les filtres numériques( http://fr.wikipedia.org/wiki/Filtre_num%C3%A9rique )

Le dac discret utilise de très petites résistances de surface de précision (0.01% / 0.02% / 0.05%). c'est grâce à ce type de résistances que les coût ont pu rester abordable, contrairement au Vishnay Z-Foil d'un totaldac.

Sign Magnitude dac comme les dacs de chez MSB: http://www.msbtech.com/support/How_DACs_Work.php

Mise à jour

La mise à jour du firmware se fera par JTAG - il faudra donc une interface usb ⇔ jtag ToBeConfirmed: il est possible qu'il faille une interface “compatible xilinx” - 30 $ mini: ( http://fr.aliexpress.com/item/Free-Shipping-New-2Sets-Xilinx-Platform-Jtag-USB-Download-Cable-Programmers-for-FPGA-CPLD-C-Mod/1906054505.html ).

Frequency Response, Impulse Response and Square Wave:

The DAC is bit correct and FAST thanks to the low capacitance compact SMT design. Only limited by the programmable digital filters, a 270 Khz 1st order bessel LPF in output of the R-2R resistor chains and clock speed. A max clock of 100 Mhz will give 6 Msps, although I'm planning to operate at 1.5 or 3 Msps. I will make more measurements, but are limited by equipment available. Want to do your own filters ? Go to t-filter.appspot.com/fir/index.html, get the filter parameters and wrap them in a header, then download to DAC. Want no filters ? Just a setting.


The board just need data with bitclock, no other input clocks needed. There is a Si514 precision programmable clock generator. The STM32 uC will measure input clock and adjust the Si514 as needed, with data buffered in FIFO, resulting in low jitter bit perfect audio data no matter the input….


As I stated, first measurement was even better than expected, didn't really know upfront what the result would be, but remember that THD is RMS measurements. A regular DAC feed by the two’s complement code has the problem that zero crossing goes from all zero'es to all ones's, meaning the distortion goes up at lower levels. The sign magnitude DAC architecture basically is two DAC's, one for the positive signal and one for the negative signal, resulting in constant distortion at all levels. T.ex. with a -60 db signal, the 10 most significant bits stays at GND for both the negative and positive DAC sections, not the constant switching of all bits…. It's not something I invented, Burr Brown did it with their Colinear chips, starting with the PCM63…. And my DAC is actually physically two R-2R strings, one with +4V ref and one with -4V reference (of course very low noise and with very precise tracking), connected together at the output which can be done as a R-2R network has constant output impedance. I also use LVC595 chips as drivers, those have about 13R output impedance at 4V, both positive and negative output fets (I measured some sample parts). I have R as 4K99, 2R is then 10K0 with 3.01M parallel to adjust for driver impedance.

Dust or other environmental issues:

The boards will be manufactured to industrial standards, and due to the low impedance everywhere I don't see any need to go further….

Volume control:

First plan is to just take a std potentiometer and connect to a ADC port on the STM32F030 uC, convert to digital and feed to the FPGA. An encoder is a possibility, GPIO bits are available on a connector, just a question of firmware. Serial port is also available, will be used for control and firmware updates.

Output buffers:

As already said, output drivers can be bypassed, the “raw” R-2R DAC outputs before buffering are available on connector J7, at line level voltage and low impedance. Connect it directly to a power amplifier, a tube buffer, or anything else you prefer…. I like balanced signal so there is an onboard balanced output driver. Later on I might look into doing a version with discrete non NFB output drivers, already have it in my CAD systems….

0.01% version:

Was originally planning for the 0.05% resistor version first, due to leadtime of parts. Will now also put priority to get 0.02% resistor version at the same time. I personally don't see the big need for the 0.01% resistor version, the sign magnitude architecture lower the requirement for resistor precision. But I will look into it, has calculated the 0.01% resistor version to USD 350. And all pricing is for complete and tested board, without connectors mounted so you have flexibility.


3.2“ x 5.8” (81 x 147 mm), two PCB mounted XLR connectors on one side for the balanced output driver.


Takes 2 x 7-15V DC or AC. Designed for single 2 x 7-8V 5W toroid transformer.